1.

Suh, J., McMahon, J., Crago, S., and Kang, D., “Optimization of Memory Allocation in VSIPL”, Eleventh High Performance Embedded Computing Workshop, September 2007. Available at www.ll.mit.edu/HPEC/agendas/proc07/agenda.html.

2.

Garrett, A., and Skjellum, A., “Extending the VSIPL Standard to Other Precisions: Gaining the Full Performance of Current Processors”, Tenth High Performance Embedded Computing Workshop, September 2006. Available at www.ll.mit.edu/HPEC/agendas/proc06/agenda.html.

3.

Hsu, C.-J., and Bhattacharyya, S., “Integrating VSIPL Support in the Dataflow Interchange Format”, Ninth High Performance Embedded Computing Workshop, September 2005. Available at www.ll.mit.edu/HPEC/agendas/proc05/agenda.html.

4.

Richards, M., Campbell, D., Judd, R., Lebak, J., and Pancoast, R., “Development Status of the Vector, Signal, and Image Processing Library (VSIPL)”, Sixth High Performance Embedded Computing Workshop, September 2002. Available at www.ll.mit.edu/HPEC/agendas/agenda02.html

5.

Sacco, S., “VSIPL, from API to Product”, Sixth High Performance Embedded Computing Workshop, September 2002. Available at www.ll.mit.edu/HPEC/agendas/agenda02.html.

6.

Skjellum, A., and Boudreaux, G., “Advanced VSIPL Computations Using C++”, Fifth High Performance Embedded Computing Workshop, November 2001.

7.

Skjellum, A., Boudreaux, G., Campbell, T., Schakelford, W., and Cohl, H., “VSIPL/ERI: Enhanced Reference Implementation of the Core VSIPL Library”, Fifth High Performance Embedded Computing Workshop, November 2001.

8.

Richards, M., Judd, R., Lebak, J., Pancoast, R., and Campbell, D., “Status of the Vector, Signal, and Image Processing Library (VSIPL)”, Fifth High Performance Embedded Computing Workshop, November 2001.

9.

Janka, R., Judd, R., Lebak, J., Richards, M., and Campbell, D., “VSIPL: an object-based open standard API for vector, signal, and image processing”, Proceedings 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '01), Volume 2, 7-11 May 2001, Page(s):949 – 952.

10.

Sheynin, Y. and Novoselova, A., “Object-orientation in parallel VSIPL architecture”, Proceedings Fourth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing, 2001 (ISORC – 2001), 2-4 May 2001, Page(s):277 – 280.

11.

Janka, R., Judd, R., Lebak, J., and Richards, M., “The Vector, Signal, and Image Processing Library (VSIPL): Emerging Implementations and Further Development”, Fourth High Performance Embedded Computing Workshop, September 2000.

12.

Paavola, S., “Implementing VSIPL Using Intelligent Compiler Technology”, Fourth High Performance Embedded Computing Workshop, September 2000.

13.

Teachey, R., Chin, B., Donadeo, A., Faix, G, and Pancoast, E., “COTS Software Portability Standards and VSIPL Benchmarks”, Fourth High Performance Embedded Computing Workshop, September 2000.

14.

Janka, R., Judd, R., Lebak, J., Richards, M., and Schwartz, D., “API and Product Status of the v1.0 Vector, Signal, and Image Processing Library (VSIPL)”, Fourth High Performance Embedded Computing Workshop, September 1999.

15.

Skjellum, A., “VSI/Pro™: A Commercial Implementation of the VSIPL Standard”, Fourth High Performance Embedded Computing Workshop, September 1999.

16.

Schwartz, D., “Vector, Signal & Image Processing Standardization for Embedded Systems: VSIP 1.0 API”, Third High Performance Embedded Computing Workshop, September 1998.

17.

Schwartz, D., “VSIP: A Standard API for Vector Signal and Image Processing”, Second High Performance Embedded Computing Workshop, September 1997.

....

1.

Moore, N., Conti, A., Leeser, M., and King, L.S., “Vforce: An Extensible Framework for Reconfigurable Supercomputing”, Computer, Volume 40, Issue 3, March 2007, Page(s):39 – 49.

2.

Mitchell, M., “Inside the VSIPL++ API”, Dr. Dobb’s Journal, Volume 31, Number 10, Page(s) 63-9, Oct. 2006.

3.

Bergmann, J., and Oldham, J., “VSIPL++: A Signal Processing Library Scaling with Moore’s Law”, Ninth High Performance Embedded Computing Workshop, September 2005. Available at www.ll.mit.edu/HPEC/agendas/proc05/agenda.html.

4.

Bergmann, J., Mitchell, M., Seefeld, S., Weingberg, Z., Myers, N., and Pancoast, R., “VSIPL++Pro – A High-Performance VSIPL++ Implementation”, Ninth High Performance Embedded Computing Workshop, September 2005. Available at www.ll.mit.edu/HPEC/agendas/proc05/agenda.html.

5.

Mitchell, M., and Oldham, J., “VSIPL++ Parallel Performance”, Eighth High Performance Embedded Computing Workshop, September 2004. Available at www.ll.mit.edu/HPEC/agenda04.htm.

6.

Mitchell, M., Oldham, J., and Sidwell, N., “VSIPL++ Serial and Parallel Performance”, Seventh High Performance Embedded Computing Workshop, September 2003. Available at www.ll.mit.edu/HPEC/agenda03.htm.

7.

Mitchell, M., and Oldham, J., “VSIPL++: Intuitive Programming Using C++ Templates”, Sixth High Performance Embedded Computing Workshop, September 2002. Available at www.ll.mit.edu/HPEC/agendas/agenda02.html.

1.

Lebak, J., Kepner, J., Hoffmann, H., and Rutledge, E., “Parallel VSIPL++: An Open Standard Software Library for High-Performance Parallel Signal Processing”, Proceedings of the IEEE, Volume 93, Issue 2, Feb. 2005, Page(s):313 – 330.

2.

Campbell, D., “The High Performance Embedded Computing Software Initiative: C++ and Parallelism Extensions to the Vector, Signal, and Image Processing Library Standard”, Proceedings Users Group Conference, 2005.

3.

Campbell, D., “The high performance embedded computing software initiative: C++ and parallelism extensions to the vector, signal, and image processing library standard”, Proceedings Users Group Conference, 2004.

4.

Mitchell, M., Oldham, J., and Sidwell, N., “VSIPL++ Serial and Parallel Performance”, Seventh High Performance Embedded Computing Workshop, September 2003. Available at www.ll.mit.edu/HPEC/agenda03.htm.

1.

McCoy, D., Moses, B., Seefeld, S., LeBlanc, M., and Bergmann, J., “Sourcery VSIPL++ for NVIDIA CUDA GPUs”, Thirteenth High Performance Embedded Computing Workshop, September 2009. Available at www.ll.mit.edu/HPEC/agendas/proc09/agenda.html.

2.

Kerr, A., Campbell, D., and Richards, M., “GPU VSIPL: Core and Beyond”, Thirteenth High Performance Embedded Computing Workshop, September 2009. Available at www.ll.mit.edu/HPEC/agendas/proc09/agenda.html.

3.

Moses, B., Bergmann, J., Seefeld, S., McCoy, D., and LeBlanc, M., “A General Framework for Multicore Programming with Sourcery VSIPL++”, Twelfth High Performance Embedded Computing Workshop, September 2008. Available at www.ll.mit.edu/HPEC/agendas/proc08/agenda.html.

4.

Kerr, A., Campbell, D., Richards, M., and Davis, M., “GPU VSIPL: High-Performance VSIPL Implementation for GPUs”, Twelfth High Performance Embedded Computing Workshop, September 2008. Available at www.ll.mit.edu/HPEC/agendas/proc08/agenda.html.

5.

Hahn Kim, Rutledge, E., Sacco, S., Mohindra, S., Marzilli, M., Kepner, J., Haney, R., Daly, J., and Bliss, N., “PVTOL: Providing Productivity, Performance and Portability to DoD Signal Processing Applications on Multicore Processors”, DoD HPCMP Users Group Conference, 2008, 14-17 July 2008, Page(s):327 – 333.

6.

Bergmann, J., Mitchell, M., McCoy, D., Seefeld, S., Salama, A., Christensen, F., and Steck, T., “Sourcery VSIPL++ for the Cell/B.E.”, Eleventh High Performance Embedded Computing Workshop, September 2007. Available at www.ll.mit.edu/HPEC/agendas/proc07/agenda.html.

7.

Campbell, D., “VSIPL++ Acceleration Using Commodity Graphics Processors”, Tenth High Performance Embedded Computing Workshop, September 2006. Available at www.ll.mit.edu/HPEC/agendas/proc06/agenda.html.

8.

Campbell, D., “VSIPL++ Acceleration Using Commodity Graphics Processors”, HPCMP Users Group Conference, June 2006, Page(s):315 – 320.

....

1.

Moore, N., Conti, A., Leeser, M., and King, L.S., “Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable Hardware”, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2007 (FCCM 2007), 23-25 April 2007, Page(s):229 – 238.

2.

Leeser, M., Conti, A., Moore, and King, L.S., “VFORCE: VSIPL++ for Reconfigurable Computing Environments”, Tenth High Performance Embedded Computing Workshop, September 2006. Available at www.ll.mit.edu/HPEC/agendas/proc06/agenda.html.

3.

Devlin, M., Bruce, R., and Marshall, S., “Implementation of Floating-Point VSIPL Functions on FPGA-Based Reconfigurable Computers Using High-Level Languages”, Ninth High Performance Embedded Computing Workshop, September 2005. Available at www.ll.mit.edu/HPEC/agendas/proc05/agenda.html.

4.

Cordes, B., and Leeser, M., “An FPGA API for VSIPL++”, Ninth High Performance Embedded Computing Workshop, September 2005. Available at www.ll.mit.edu/HPEC/agendas/proc05/agenda.html.

5.

Bergmann, J., Bronowicz, P., and Emeny, S., “VSIPL++/FPGA Design Methodology”, Seventh High Performance Embedded Computing Workshop, September 2003. Available at www.ll.mit.edu/HPEC/agenda03.htm.

1.

Bergmann, J., LeBlanc, M., McCoy, D., Moses, B., and Seefeld, S., “Scalable SAR with Sourcery VSIPL++ for the Cell/B.E.”, Twelfth High Performance Embedded Computing Workshop, September 2008. Available at www.ll.mit.edu/HPEC/agendas/proc08/agenda.html.

2.

Steck, T., Pancoast, R., Taliaferro, E., and Bergmann, J., “Defense Applications Implemented Utilizing the Parallel Processing Features of Sourcery VSIPL++”, Eleventh High Performance Embedded Computing Workshop, September 2007. Available at www.ll.mit.edu/HPEC/agendas/proc07/agenda.html.

3.

Steck, T., “A Comparison of VSIPL++ Performance to VSIPL and Mercury SAL”, Tenth High Performance Embedded Computing Workshop, September 2006. Available at www.ll.mit.edu/HPEC/agendas/proc06/agenda.html.

4.

McCoy, D., Bergmann, J., and Seefeld, S., “Sourcery VSIPL++ on the Cell Broadband Engine: A Fused Fast Convolution Example”, DoD High Performance Computing Modernization Program Users Group Conference, 2007, 18-21 June 2007, Page(s):283 – 288.

5.

Daly, K., Cook, R., Pancoast, R., Crago, S., French, M., Singh, K., and Suh, J., “Using VSIPL as an Embedded DoD Application Programming Interface (API) on DARPA Polymorphous Computing Architectures (PCA)”, Tenth High Performance Embedded Computing Workshop, September 2006. Available at www.ll.mit.edu/HPEC/agendas/proc06/agenda.html.

6.

Bergmann, J., McCoy, D., Seefeld, S., and Mitchell, M., “Taking the HPEC Challenge with VSIPL++”, Tenth High Performance Embedded Computing Workshop, September 2006. Available at www.ll.mit.edu/HPEC/agendas/proc06/agenda.html.

7.

Bergmann, J. and McCoy, D., “Sourcery VSIPL++ HPEC Benchmark Performance”, HPCMP Users Group Conference, June 2006, Page(s):308 – 314.

8.

Cook, J., Crago, S., Morda, L., Pancoast, R., and Suh, J., “Implementation of an Embedded DoD VSIPL Application on the DARPA Polymorphous Computing Architectures (PCA) RAW Processor”, Ninth High Performance Embedded Computing Workshop, September 2005. Available at www.ll.mit.edu/HPEC/agendas/proc05/agenda.html.

9.

Alford, T., Shah, V.P., Skjellum, A., Younan, N.H., and Taylor, C.D., “inAspect: interfacing Java and VSIPL applications”, Concurrency and Computation Practice & Experience, Volume 17, Number 7-8, Page(s) 919-40, June-July 2005.

10.

Cottell, D., and Judd, R., “Evaluation of the VSIPL++ Serial Specification using the DADS Beamformer”, Eighth High Performance Embedded Computing Workshop, September 2004. Available at www.ll.mit.edu/HPEC/agenda04.htm.

11.

Chase, B., Leimbach, D., Pancoast, R., Skjellum, A, and Wu, W., “Pulse Compression Made Easy with VSIPL++”, Eighth High Performance Embedded Computing Workshop, September 2004. Available at www.ll.mit.edu/HPEC/agenda04.htm.

12.

Chase, B., Skjellum, A, and Wu, W., “VSIPL for Diverse Architectures (Pentium 4 to DSPs)”, Seventh High Performance Embedded Computing Workshop, September 2003. Available at www.ll.mit.edu/HPEC/agenda03.htm.

13.

Averill, D., “Successful VSIPL Software Application Migration- A Case Study: NATO Seasparrow Illumination Radar Signal Processing”, Seventh High Performance Embedded Computing Workshop, September 2003. Available at www.ll.mit.edu/HPEC/agenda03.htm.

14.

Kepner, J., “A multi-threaded fast convolver for dynamically parallel image filtering”, Journal of Parallel and Distributed Computing, Volume 63, Number 3, Page(s) 360-72, March 2003.

15.

Walsh, B., Hunziker, J., Maese, T., Mazur, W., and Sabin, W., “National Weather Radar Testbed System Implemented Using COTS and VSIPL”, Sixth High Performance Embedded Computing Workshop, September 2002. Available at www.ll.mit.edu/HPEC/agendas/agenda02.html.

16.

Kepner, J., “Integration of VSIPL and OpenMP into a Parallel Image Processing Environment”, Fourth High Performance Embedded Computing Workshop, September 2000.

17.

Judd, R., “A Parallel Algorithm for Matched Field Processing Using MPI and VSIPL”, Fourth High Performance Embedded Computing Workshop, September 2000.

18.

Janka, R.S., and Wills, L.M., “Combining virtual benchmarking with rapid system prototyping for real-time embedded multiprocessor signal processing system codesign”, Proceedings 11th International Workshop on Rapid System Prototyping, 2000 (RSP 2000), 21-23 June 2000, Page(s):20 – 25.

19.

Janka, R.S., and Wills, L.M., “A novel codesign methodology for real-time embedded COTS multiprocessor-based signal processing systems”, Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000 (CODES 2000), Page(s):157 – 161.